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| THURSDAY, June 10, 2004, 8:30 AM - 10:00 AM | Room: 6C | ||
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TOPIC AREA: PHYSICAL CIRCUIT DESIGN | ||
| SESSION 38 | |||
| Floorplanning | |||
| Chair: Malgorzata Marek-Sadowska - Univ. of California, Santa Barbara, CA | |||
| Organizers: Chung-Kuan Cheng, Frank M. Johannes | |||
| The session advocates floorplanning for architecture-level and layout optimization. In the first paper, a microarchitectural floorplanner is presented that considers both the impact of wire delay and architectural behavior. The second paper increases instructions per cycle using a trajectory piece-wise linear model. A representation to tackle the floorplanning of triangular objects that achieves efficient area utilization is introduced in the third paper. | |||
 38.1 |
Profile-Guided Microarchitectural Floorplanning for Deep Submicron Processor Design |
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| Speaker(s): | Mongkol Ekpanyapong - Georgia Institute of Tech., Atlanta, GA | ||
| Author(s): | Mongkol Ekpanyapong - Georgia Institute of Tech., Atlanta, GA Jacob R. Minz - Georgia Institute of Tech., Atlanta, GA Thaisiri Watewai - Univ. of California, Berkeley, CA Hsien-Hsin S. Lee - Georgia Institute of Tech., Atlanta, GA Sung Kyu Lim - Georgia Institute of Tech., Atlanta, GA | ||
| 38.2 | Floorplanning Optimization with Trajectory Piecewise-Linear Model for Pipelined Interconnects | ||
| Speaker(s): | Changbo Long - Univ. of California, Los Angeles, CA | ||
| Author(s): | Changbo Long - Univ. of California, Los Angeles, CA Lucanus J. Simonson - Univ. of California, Los Angeles, CA Weiping Liao - Univ. of California, Los Angeles, CA Lei He - Univ. of California, Los Angeles, CA | ||
| 38.3 | A Packing Algorithm for Non-Manhattan Hexagon/Triangle Placement by Using an Adaptive O-Tree Representation | ||
| Speaker(s): | Chunghui Li - , | ||
| Author(s): | Jing Li - Univ. of Electronic Sci. & Tech. of China, Chengdu, China Bo Yang - Univ. of Electronic Sci. & Tech. of China, Chengdu, China Tan Yan - Univ. of Electronic Sci. & Tech. of China, Chengdu, China Juebang Yu - , China Chunhui Li - Cadence Design Systems Inc., San Jose, CA | ||
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